The embodiments of the invention generally relate to transistor structures and more particularly to fin-type field effect transistors (FinFET) that utilize gate straps above the gate conductors.
Within FinFETs and other similar structures, fin edge capacitance and corner parasitic reactions can degrade performance of the FinFET Technology. In order to address such issues, the present invention is directed to a semiconductor structure, which includes FinFET devices having a gate strapping plug between adjacent fins, recessed below the top of a cap on the fins. This structure reduces the outer fringe capacitance. More specifically, with embodiments herein, the fin-type field effect transistor (FinFET) structure begins with a substrate and a fin having a bottom positioned on the top surface of the substrate. The fin has a “fin length” running parallel to the top surface of the substrate, a “fin height” above the top surface of the substrate that is less than the fin length, and a “fin width” running parallel to the top surface of the substrate and running perpendicular to the fin length.
The fin is a relatively narrow width, relatively tall height structure that protrudes from the top surface of the substrate. Therefore, the fin width is less than the fin height. A fin cap is positioned on the top of the fin and runs along the fin. The fin cap has a fin cap width equal to the fin width, and fin cap height that is less than the fin height.
A gate conductor is positioned on the top surface of the substrate. The gate conductor has a “gate conductor length” running parallel to the top of the substrate that is perpendicular to the fin length such that the gate conductor intersects the fin. The gate conductor has a gate conductor height above the top surface of the substrate that is greater than the fin height, yet that is less than the height that the top of fin cap is positioned above the top surface of the substrate.
A gate strap is positioned on the top of the gate conductor and runs along the gate conductor. The gate strap has a “gate strap width” equal to the gate conductor width. The top of the gate strap is positioned a greater height above the top surface of the substrate than the top of the fin cap. The top of the portion of the gate strap that crosses the fin cap has a greater height above the top surface of the substrate than top portions of other regions of the gate strap. Further, the material of the gate strap can have a different work function than a material of the gate conductor.
As with conventional FinFET structures, an insulator (e.g., gate oxide) separates the gate conductor and the gate strap from the fin and the fin cap. Further, the region of the fin that is positioned below the gate conductor comprises a semiconductor. Further, the FinFET structure can include multiple fins and fin caps, in which case the gate conductor would fill in the space between the gate conductors and comprise a gateplug.
These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications.